The present invention relates to a semiconductor design technology, and more particularly, to a spread spectrum clock generator.
Recently, vigorous researches are being made on reduction of electromagnetic interference (EMI) caused by an electromagnetic radiation in a semiconductor device such as a double data rate synchronous DRAM (DDR SDRAM). The frequency of an operation clock increases and the interconnection lengths in an electronic circuit and a substrate decreases with the rapid development of the semiconductor technology, causing rapid increase of the EMI generation. In addition, because the fine and highly integrated interconnections also serve as antennas, the electromagnetic radiation increases further and thus the EMI generation also increases further.
A spread spectrum clock generator (SSCG) is a device for reducing the EMI generation. The spread spectrum clock generator sequentially modulates a frequency of an operation clock so that the energy concentrated on a specific frequency range is uniformly distributed over a much wider frequency range.
FIG. 1 is a circuit diagram illustrating a conventional spread spectrum clock generator.
Referring to FIG. 1, the conventional spread spectrum clock generator includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, a second NMOS transistor NM2, a first falling loading unit 110, a second falling loading unit 170, a first rising loading unit 130, and a second rising loading unit 150. The first PMOS transistor PM1 and the first NMOS transistor NM1 have gates receiving a fixed clock CLK_F of a constant frequency. The first falling loading unit 110 is connected between the first PMOS transistor PM1 and a first node A, whereas the first rising loading unit 130 is connected between the first NMOS transistor NM1 and the first node A. The second PMOS transistor PM2 and the second NMOS transistor NM2 have gates coupled to the first node A. The second rising loading unit 150 is connected between the second PMOS transistor PM2 and an output terminal for outputting a modulated clock CLK_M. The second falling loading unit 170 is connected between the second NMOS transistor NM2 and the output terminal.
The first rising loading unit 130 and the second rising loading unit 150 delay a rising edge of the fixed clock CLK_F by a delay time corresponding to a predetermined number of unit delay steps. The first falling loading unit 110 and the second falling loading unit 170 delay a falling edge of the fixed clock CLK_F by a delay time corresponding to a predetermined number of unit delay steps.
That is, the loading units 110, 130, 150 and 170 delay the rising edge and the falling edge of the fixed clock CLK_F by the delay time corresponding to the predetermined number of unit delay steps, thereby sequentially modifying the fixed clock CLK_F while keeping a duty ratio at 50:50.
FIG. 2 is a circuit diagram illustrating a circuit configuration of the first rising loading unit 130 of the typical spread spectrum clock generator shown in FIG. 1.
All the loading units 110, 130, 150 and 170 may have substantially the same circuit configuration. However, to a different loading unit may be input a different set of delay step control signals CTR0, CTR1, CTR2, CTR3, CTR4, CTR5, CTR6 and CTR7.
Referring to FIG. 2, the first rising loading unit 130 has eight resistors R0, R1, R2, R3, R4, R5 R6 and R7 and eight transfer gates TG0, TG1, TG2, TG3, TG4, TG5, TG6 and TG7. All the eight resistors have the same resistance. The transfer gates TG0, TG1, TG2, TG3, TG4, TG5, TG6 and TG7 correspond to the respective resistors R0, R1, R2, R3, R4, R5, R6 and R7. The transfer gates TG0, TG1, TG2, TG3, TG4, TG5, TG6 and TG7 allow the respective resistors R0, R1, R2, R3, R4, R5, R6 and R7 to be bypassed in response to the respective delay step control signals CTR0, CTR1, CTR2, CTR3, CTR4, CTR5, CTR6 and CTR7.
Therefore, the first rising loading unit 130 delays the clock edge of the fixed clock CLK_F by a delay time corresponding to the number of the resistors which the fixed clock CLK_F have passed through according to the delay step control signals CTR0, CTR1, CTR2, CTR3, CTR4, CTR5, CTR6 and CTR7.
FIGS. 3A to 3C are timing diagrams illustrating a time delay performed by the first rising loading unit 130 of the conventional spread spectrum clock generator shown in FIG. 1.
FIG. 3A shows a timing diagram of the modulated clock CLK_M generated by delaying the fixed clock CLK_F by only a basic delay time to. FIG. 3B shows a timing diagram of the modulated clock CLK_M generated by delaying the fixed clock CLK_F by a basic delay time to and a delay time t corresponding to one unit delay step. FIG. 3C shows a timing diagram of the modulated clock CLK_M generated by delaying the fixed clock CLK_F by a basic delay time to and a delay time 5t corresponding to five unit delay steps.
The delay time corresponding to the number of the unit delay steps refers to a total delay time performed by the first rising loading unit 130.
FIG. 4 illustrates the modulated clock CLK_M generated by delaying the fixed clock CLK_F by delay times determined at the loading units 110, 130, 150 and 170 of the conventional spread spectrum clock generator shown in FIG. 1.
Referring to FIG. 4, there are shown the fixed clock CLK_F, the modulated clock CLK_M, the number of unit delay steps R applied to the rising edge of the fixed clock CLK_F, the number of unit delay steps F applied to the falling edge of the fixed clock CLK_F and a cycle of the modulated clock CLK_M. For convenience, the basic delay time to described above with reference to FIG. 3 is disregarded and the delay time corresponding to one unit delay step is supposed to be t.
A first cycle of the modulated clock CLK_M has the same cycle as that of the fixed clock CLK_F, i.e., period T, because only the basic delay time is applied to rising and falling edges of the fixed clock CLK_F. One unit delay step is applied to a falling edge of a second cycle of the fixed clock CLK_F and two unit delay steps are applied to a rising edge of a third cycle of the fixed clock CLK_F so that the second cycle of the modulated clock CLK_M has a cycle of T+2t. Four unit delay steps are applied to a falling edge of the third cycle of the fixed clock CLK_F and six unit delay steps are applied to a rising edge of a fourth cycle of the fixed clock CLK_F, so that the third cycle of the modulated clock CLK_M has a cycle of T+4t. Therefore, cycles of the modulated clock CLK_M increase gradually as T→T+2t→T+4t.
Then, seven unit delay steps are applied to a falling edge of the fourth cycle of the fixed clock CLK_F and eight unit delay steps are applied to a rising edge of a fifth cycle of the fixed clock CLK_F, so that the fourth cycle of the modulated clock CLK_M has a cycle of T+2t. Eight unit delay steps are applied to a falling edge of the fifth cycle of the fixed clock CLK_F and eight unit delay steps are applied to a rising edge of a sixth cycle of the fixed clock CLK_F, so that the fifth cycle of the modulated clock CLK_M again has a cycle of T. Accordingly, cycles of the modulated clock CLK_M decrease again.
As described above, a predetermined number of unit delay steps are applied to the rising and falling edges of the fixed clock CLK_F so that the modulated clock CLK_M has a cycle which sequentially changes as T→T+2t→T+4t→T+2t→T→T−2t→T−4t→T−2t→T while keeping its duty ratio of 50:50. This provides the modulated clock CLK_M with a characteristic of a reduced generation of EMI.
However, in such a configuration, a modulation rate of the modulated clock CLK_M in comparison with the fixed clock CLK_F cannot be changed because the delay time corresponding to one unit delay step is fixed. Accordingly, in order to further reduce an EMI generation, a spread spectrum clock generator which can provide the clock with a more appropriate modulation rate is needed.